11 days old

Engineer Consultant

San Jose, CA 95134
  • Job Code
  • Payrate
    $45 To $55


Route and validate silicon package substrate designs critical to high speed networking product requirements. It is critical to understand manufacturing design rules, Signal Integrity and Power Integrity requirements to minimize package iterations and create working designs.


Setup the design, create routing standards and implement package route to meet the rules required for very high speed serdes and large pin count devices.

The role will require working with package and Signal Integrity engineers. Iteration with pcb, connector, and asic team may be required. Focus will be primarily on flip chip packages and heterogeneous integration chip package design.

Capability of understanding and driving to milestones to make development successful.

A complete knowledge of packaging materials and material properties is needed. The knowledge of 2.1D, 2.5D and interposer integration is a plus.


A working knowledge of Cadence Allegro Packaging Design (APD) is a must. Experience with v17.2 of APD and Cadence System in Package (SiP) is a plus. Additional knowledge of Ansys HFSS, SiWave, Icepak and Cadence XtractIM/PowerSI will be beneficial.


Degree in Electrical Engineering or related field, or equivalent experience.

7 or more years in the industry with packaging development.

Experience with several high pin count, high power and high speed packages.

Strong communication, problem solving, interpersonal and presentation/documentation skills.


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Engineer Consultant

Randstad Technologies
San Jose, CA 95134

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Randstad Technologies
San Jose, CA

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