12 days old
2017-11-292017-12-27

DFT (Design for Test Engineer)

Cary, NC 27513
  • Job Code
    589682

We have a one year, renewable contract for a Design for Test Engineer with a client of ours in Raleigh, NC.


Our SoC Design Team is currently seeking candidates for a temporary position working DFT on high performance, highly integrated Server SoCs. The assignment will be a mix of activities, including supporting DFT on an existing server SOC, creating documentation material, debugging ATPG and memory BIST vectors, assisting in silicon debug of DFT test vectors, performing scan insertion on cores, and running memory BIST flows on cores. The ideal candidate has a wide range of experience with DFT topics as opposed to a narrow focus on a single item. Further, the ideal candidate has experience supporting customers remotely and has a strong understanding of vector debug on ATE, be it an ATPG vector or a functional vector that boots one or more CPU cores. Though not required to operate the ATE the candidate must understand the basics of ATE operation and be able to advise as needed and assist in debugging failing patterns. This means the candidate would be able to list for a test engineer a list of experiments to perform. Because not all the work is debugging patterns on the ATE the candidate will also have activities that involve scan insertion, ATPG/DRC, coverage analysis, ATPG vector simulation including SAF and TDF, and memory BIST activities. Responsibilities: Implementation of DFT/DFD (design for test/design for debug) techniques for high performance, highly integrated SoCs. Work with design teams to improve low coverage on designs to desired target. Generate ATE patterns. Work with Test Engineers during pattern bring up and debug.


Minimum Qualifications:


5 years of experience in many of the following areas is required: - DFT/DFD/DFM techniques for complex SoCs - Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models - Scan Insertion, ATPG, Scan Compression, At-speed Testing - Scan Insertion using DFTC or equivalent - Industry standard ATPG tools like Mentor TestKompress, Synopsys TetraMax, or Cadence Encounter Test - Experience with LVmemBIST or Synopsys STAR BIST - Logic design, Verilog RTL and verification - Some scripting in Perl and Tcl - Industry standard simulation tools such as VCS, Questasim or NCVerilog - Silicon bring-up, debug, and validation of DFT features on ATE


Preferred Qualifications:


7 years of experience in many of the following areas is required: - DFT/DFD/DFM techniques for complex SoCs - Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models - Scan Insertion, ATPG, Scan Compression, At-speed Testing - Scan Insertion using DFTC or equivalent - Industry standard ATPG tools like Mentor TestKompress, Synopsys TetraMax, or Cadence Encounter Test - Experience with LVmemBIST or Synopsys STAR BIST - Logic design, Verilog RTL and verification - Some scripting in Perl and Tcl - Industry standard simulation tools such as VCS, Questasim or NCVerilog - Silicon bring-up, debug, and validation of DFT features on ATE


Education:


BSEE and/or MSEE

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DFT (Design for Test Engineer)

Randstad Technologies
Cary, NC 27513

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DFT (Design for Test Engineer)

Randstad Technologies
Cary, NC
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